This invention relates generally to partial write to a memory, and more particularly to a partial write control apparatus for a memory equipped with a high speed operation mode which permits access to a plurality of addressed locations in a single access cycle.
A rewrite or update processing of only part of an access unit of stored information (which will be hereinafter represented by a word) is referred to as "partial write". The partial write processing consists of a read operation of an object word, an operation which replaces part of the word thus read by new data to form a partially updated word and a write operation which writes the partially updated word. Therefore, it needs a longer time than an ordinary write operation.
Japanese Patent Laid-Open No. 145428/1978 discloses a method which shortens the time necessary for partial write. This method utilizes a shift register group which is disposed inside a memory controller in order to hold the accepted access request information (such as control information, data and an address) and has a length corresponding to a memory cycle time, so that when the read operation of the object word of partial write is completed, the corresponding access request information is returned to the input stage of the shift register group together with the word that has been read and updated, thereby automatically registering a write request. This shortens the period of time in which the access requester unit is involved in the operation of the memory.
In the field of dynamic RAMs (Random Access Memories), on the other hand, a memory device equipped with a high speed operation mode which permits access to a plurality of word locations in a single access cycle caused by one RAS signal is well known. In a mode called a "page mode", for example, access en bloc to a plurality of addresses having a common row address is possible by providing sequentially different column addresses under a certain row address. In a mode called a "nibble mode", on the other hand, access en bloc to up to four continuous addresses is possible as the address value is counted up inside the memory after one set of the row address and the column address is given. However, an efficient partial write mechanism for a memory constituted by these types of elements has not yet been developed sufficiently. The method disclosed in the prior art reference described above is for a memory device of such a type wherein each access operation is carried out for a single word.
A series of words resident at continuous addresses must often be processed in practical data processing. Needless to say, the high speed operation modes described above are generally helpful to improve the speed of processing of this type, but a special mechanism is necessary in order to write efficiently a series of words containing words for which partial write is necessary. In conventional read/write mechanisms, the word for which partial write is necessary must be separated from the other words and processed singly by a separate read/write operation, implying that the advantage of the high speed operation modes described above is not fully utilized.